march 1998 f dc63 3 n n -channel enhancement mode field effect transistor general description features absolute maximum ratings t a = 25c unless otherwise noted symbol parameter f dc63 3 n units v dss drain-source voltage 30 v v gss gate-source voltage - continuous 8 v i d drain current - continuous (note 1a) 5.2 a - pulsed 16 p d maximum power dissipation ( note 1a) 1.6 w (note 1b) 0.8 t j ,t stg operating and storage temperature range -55 to 15 0 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 78 c/w r q jc thermal resistance, junction-to-case (note 1) 30 c/w fdc63 3n rev.c this n -channel enhancement mode power field effect transistors is produced using fairchild's proprietary, high cell density, dmos technology. this very high density process is tailored to minimize on-state resistance. these devices are particularly suited for low voltage applications in notebook computers, portable phones, pcmica cards, and other battery powered circuits where fast switching,low in-line power loss and resistance to transients are needed in a very small outline surface mount package. 5.2 a, 3 0 v. ?r ds(on ) = 0.042 w @ v gs = 4.5 v r ds(on ) = 0.054 w @ v gs = 2.5 v . supersot tm -6 package design using copper lead frame for superior thermal and electrical capabilities. high density cell design for extremely low r ds(on) . exceptional on-resistance and maximum dc current capability. soic-16 sot-23 supersot t m -8 so-8 sot-223 supersot t m -6 3 5 6 4 1 2 3 d d d s d g supersot -6 tm .633 pin 1 ? 1998 fairchild semiconductor corporation
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 30 v d bv dss / d t j breakdown voltage temp. coefficient i d = 250 a , referenced to 25 o c 42 mv/ o c i dss zero gate voltage drain current v ds = 24 v , v gs = 0 v 1 a t j = 55 o c 10 a i gssf gate - body leakage, forward v gs = 8 v, v ds = 0 v 100 na i gssr gate - body leakage, reverse v gs = -8 v, v ds = 0 v -100 na on characteristics (note 2) v gs (th) gate threshold voltage v ds = v gs , i d = 250 a 0.4 0.67 1 v d v gs(th) / d t j gate threshold voltage temp.coefficient i d = 250 a , referenced to 25 o c -2.4 mv/ o c r ds(on) static drain-source on-resistance v gs = 4.5 v, i d = 5.2 a 0.033 0.042 w t j = 125 o c 0.051 0.07 v gs = 2.5 v, i d = 4.5 a 0.043 0.054 i d (on) on-state drain current v gs = 4.5 v, v ds = 5 v 11 a g fs forward transconductance v ds = 10 v, i d = 5.2 a 15 s dynamic characteristics c iss input capacitance v ds = 10 v, v gs = 0 v, 538 pf c oss output capacitance f = 1.0 mhz 226 pf c rss reverse transfer capacitance 51 pf switching ch aracteristics (note 2 ) t d(on ) turn - on delay time v dd = 5 v, i d = 1 a, 5 12 ns t r turn - on rise time v gs = 4.5 v, r gen = 6 w 17 27 ns t d(off) turn - off delay time 25 40 ns t f turn - off fall time 5.3 11 ns q g total gate charge v ds = 10 v, i d = 5.2 a, 11 16 nc q gs gate-source charge v gs = 4.5 v 2 nc q gd gate-drain charge 2.4 nc drain-source diode characteristics i s continuous source diode current 1.3 a v sd drain-source diode forward voltage v gs = 0 v, i s = 1.3 a (note 2 ) 0.7 1.2 v t j = 125 o c 0.57 1 notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. a. 78 o c/w when mounted on a 1 in 2 pad of 2oz cu o n fr-4 board . b . 156 o c/w when mounted on a minimum pad of 2oz cu o n fr-4 board. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. fdc63 3n rev.c
fdc63 3n rev.c 0 0.5 1 1.5 2 2.5 3 0 5 10 15 20 v , drain-source voltage (v) i , drain-source current (a) v = 4.5v gs 1.5 ds d 2.0 3.0 2.5 0 5 10 15 20 0.8 1 1.2 1.4 1.6 1.8 2 i , drain current (a) drain-source on-resistance v = 2.0v gs d r , normalized ds(on) 3.0 4.5 3.5 2.5 typical electrical characteristics figure 1. on-region characteristics . figure 2. on-resistance variation with drain current and gate voltage . figure 3. on-resistance variation with temperature . figure 5 . transfer characteristics. 0 0.2 0.4 0.6 0.8 1 1.2 0.0001 0.001 0.01 0.1 1 15 v , body diode forward voltage (v) i , reverse drain current (a) 25c -55c v = 0v gs sd s t = 125c j figure 4 . on-resistance variation with gate-t o -source voltage. -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance r , normalized ds(on) j v = 4.5v gs i = 5.2a d 1 2 3 4 5 0 0.03 0.06 0.09 0.12 0.15 v , gate to source voltage (v) i = 2.5a d gs r , on-resistance (ohm) ds(on) t = 25c a t = 125c a 0 0.5 1 1.5 2 2.5 0 3 6 9 12 15 v , gate to source voltage (v) i , drain current (a) v = 5v ds gs d t = -55c j 125c 25c figure 6 . body diode forward voltage varia tion with source current and temperature.
fdc63 3n rev.c figure 10 . single pulse maximum power dissipation. 0.1 0.3 1 3 10 30 20 50 100 300 600 1300 v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0 v gs c oss c rss figure 8. capacitance characteristics . figure 7 . gate charge characteristics. figure 9. maximum safe operating area. typical electrical characteristics (continued) 0 3 6 9 12 15 0 1 2 3 4 5 q , gate charge (nc) v , gate-source voltage (v) g gs v = 5v ds 10v i = 5.2a d 15v 0.1 0.2 0.5 1 2 5 10 30 50 0.01 0.05 0.1 0.5 1 2 5 10 20 40 v , drain-source voltage (v) i , drain current (a) rds(on) limit d a dc ds 1s 100ms 10ms 1ms v = 4.5v single pulse r = see note 1b t = 25c q ja gs a 100us 0.01 0.1 1 10 100 300 0 1 2 3 4 5 single pulse time (sec) power (w) single pulse r =see note 1b t = 25c q ja a 0.00001 0.0001 0.001 0.01 0.1 1 10 100 300 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 duty cycle, d = t / t 1 2 r (t) = r(t) * r r = see note 1b t - t = p * r (t) a j p(pk) t 1 t 2 q ja q ja q ja q ja figure 11 . transient thermal response curve . thermal characterization performed using the conditions described in note 1b . transient thermal response will change depending on the circuit board design.
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